1 // Copyright 2018 The Go Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style
3 // license that can be found in the LICENSE file.
5 // Package cpu implements processor feature detection for
6 // various CPU architectures.
14 // Initialized reports whether the CPU features were initialized.
16 // For some GOOS/GOARCH combinations initialization of the CPU features depends
17 // on reading an operating specific file, e.g. /proc/self/auxv on linux/arm
18 // Initialized will report false if reading the file fails.
21 // CacheLinePad is used to pad structs to avoid false sharing.
22 type CacheLinePad struct{ _ [cacheLineSize]byte }
24 // X86 contains the supported CPU features of the
25 // current X86/AMD64 platform. If the current platform
26 // is not X86/AMD64 then all feature flags are false.
28 // X86 is padded to avoid false sharing. Further the HasAVX
29 // and HasAVX2 are only set if the OS supports XMM and YMM
30 // registers in addition to the CPUID feature bit being set.
33 HasAES bool // AES hardware implementation (AES NI)
34 HasADX bool // Multi-precision add-carry instruction extensions
35 HasAVX bool // Advanced vector extension
36 HasAVX2 bool // Advanced vector extension 2
37 HasAVX512 bool // Advanced vector extension 512
38 HasAVX512F bool // Advanced vector extension 512 Foundation Instructions
39 HasAVX512CD bool // Advanced vector extension 512 Conflict Detection Instructions
40 HasAVX512ER bool // Advanced vector extension 512 Exponential and Reciprocal Instructions
41 HasAVX512PF bool // Advanced vector extension 512 Prefetch Instructions Instructions
42 HasAVX512VL bool // Advanced vector extension 512 Vector Length Extensions
43 HasAVX512BW bool // Advanced vector extension 512 Byte and Word Instructions
44 HasAVX512DQ bool // Advanced vector extension 512 Doubleword and Quadword Instructions
45 HasAVX512IFMA bool // Advanced vector extension 512 Integer Fused Multiply Add
46 HasAVX512VBMI bool // Advanced vector extension 512 Vector Byte Manipulation Instructions
47 HasAVX5124VNNIW bool // Advanced vector extension 512 Vector Neural Network Instructions Word variable precision
48 HasAVX5124FMAPS bool // Advanced vector extension 512 Fused Multiply Accumulation Packed Single precision
49 HasAVX512VPOPCNTDQ bool // Advanced vector extension 512 Double and quad word population count instructions
50 HasAVX512VPCLMULQDQ bool // Advanced vector extension 512 Vector carry-less multiply operations
51 HasAVX512VNNI bool // Advanced vector extension 512 Vector Neural Network Instructions
52 HasAVX512GFNI bool // Advanced vector extension 512 Galois field New Instructions
53 HasAVX512VAES bool // Advanced vector extension 512 Vector AES instructions
54 HasAVX512VBMI2 bool // Advanced vector extension 512 Vector Byte Manipulation Instructions 2
55 HasAVX512BITALG bool // Advanced vector extension 512 Bit Algorithms
56 HasAVX512BF16 bool // Advanced vector extension 512 BFloat16 Instructions
57 HasBMI1 bool // Bit manipulation instruction set 1
58 HasBMI2 bool // Bit manipulation instruction set 2
59 HasERMS bool // Enhanced REP for MOVSB and STOSB
60 HasFMA bool // Fused-multiply-add instructions
61 HasOSXSAVE bool // OS supports XSAVE/XRESTOR for saving/restoring XMM registers.
62 HasPCLMULQDQ bool // PCLMULQDQ instruction - most often used for AES-GCM
63 HasPOPCNT bool // Hamming weight instruction POPCNT.
64 HasRDRAND bool // RDRAND instruction (on-chip random number generator)
65 HasRDSEED bool // RDSEED instruction (on-chip random number generator)
66 HasSSE2 bool // Streaming SIMD extension 2 (always available on amd64)
67 HasSSE3 bool // Streaming SIMD extension 3
68 HasSSSE3 bool // Supplemental streaming SIMD extension 3
69 HasSSE41 bool // Streaming SIMD extension 4 and 4.1
70 HasSSE42 bool // Streaming SIMD extension 4 and 4.2
74 // ARM64 contains the supported CPU features of the
75 // current ARMv8(aarch64) platform. If the current platform
76 // is not arm64 then all feature flags are false.
79 HasFP bool // Floating-point instruction set (always available)
80 HasASIMD bool // Advanced SIMD (always available)
81 HasEVTSTRM bool // Event stream support
82 HasAES bool // AES hardware implementation
83 HasPMULL bool // Polynomial multiplication instruction set
84 HasSHA1 bool // SHA1 hardware implementation
85 HasSHA2 bool // SHA2 hardware implementation
86 HasCRC32 bool // CRC32 hardware implementation
87 HasATOMICS bool // Atomic memory operation instruction set
88 HasFPHP bool // Half precision floating-point instruction set
89 HasASIMDHP bool // Advanced SIMD half precision instruction set
90 HasCPUID bool // CPUID identification scheme registers
91 HasASIMDRDM bool // Rounding double multiply add/subtract instruction set
92 HasJSCVT bool // Javascript conversion from floating-point to integer
93 HasFCMA bool // Floating-point multiplication and addition of complex numbers
94 HasLRCPC bool // Release Consistent processor consistent support
95 HasDCPOP bool // Persistent memory support
96 HasSHA3 bool // SHA3 hardware implementation
97 HasSM3 bool // SM3 hardware implementation
98 HasSM4 bool // SM4 hardware implementation
99 HasASIMDDP bool // Advanced SIMD double precision instruction set
100 HasSHA512 bool // SHA512 hardware implementation
101 HasSVE bool // Scalable Vector Extensions
102 HasASIMDFHM bool // Advanced SIMD multiplication FP16 to FP32
106 // ARM contains the supported CPU features of the current ARM (32-bit) platform.
107 // All feature flags are false if:
108 // 1. the current platform is not arm, or
109 // 2. the current operating system is not Linux.
112 HasSWP bool // SWP instruction support
113 HasHALF bool // Half-word load and store support
114 HasTHUMB bool // ARM Thumb instruction set
115 Has26BIT bool // Address space limited to 26-bits
116 HasFASTMUL bool // 32-bit operand, 64-bit result multiplication support
117 HasFPA bool // Floating point arithmetic support
118 HasVFP bool // Vector floating point support
119 HasEDSP bool // DSP Extensions support
120 HasJAVA bool // Java instruction set
121 HasIWMMXT bool // Intel Wireless MMX technology support
122 HasCRUNCH bool // MaverickCrunch context switching and handling
123 HasTHUMBEE bool // Thumb EE instruction set
124 HasNEON bool // NEON instruction set
125 HasVFPv3 bool // Vector floating point version 3 support
126 HasVFPv3D16 bool // Vector floating point version 3 D8-D15
127 HasTLS bool // Thread local storage support
128 HasVFPv4 bool // Vector floating point version 4 support
129 HasIDIVA bool // Integer divide instruction support in ARM mode
130 HasIDIVT bool // Integer divide instruction support in Thumb mode
131 HasVFPD32 bool // Vector floating point version 3 D15-D31
132 HasLPAE bool // Large Physical Address Extensions
133 HasEVTSTRM bool // Event stream support
134 HasAES bool // AES hardware implementation
135 HasPMULL bool // Polynomial multiplication instruction set
136 HasSHA1 bool // SHA1 hardware implementation
137 HasSHA2 bool // SHA2 hardware implementation
138 HasCRC32 bool // CRC32 hardware implementation
142 // MIPS64X contains the supported CPU features of the current mips64/mips64le
143 // platforms. If the current platform is not mips64/mips64le or the current
144 // operating system is not Linux then all feature flags are false.
147 HasMSA bool // MIPS SIMD architecture
151 // PPC64 contains the supported CPU features of the current ppc64/ppc64le platforms.
152 // If the current platform is not ppc64/ppc64le then all feature flags are false.
154 // For ppc64/ppc64le, it is safe to check only for ISA level starting on ISA v3.00,
155 // since there are no optional categories. There are some exceptions that also
156 // require kernel support to work (DARN, SCV), so there are feature bits for
157 // those as well. The minimum processor requirement is POWER8 (ISA 2.07).
158 // The struct is padded to avoid false sharing.
161 HasDARN bool // Hardware random number generator (requires kernel enablement)
162 HasSCV bool // Syscall vectored (requires kernel enablement)
163 IsPOWER8 bool // ISA v2.07 (POWER8)
164 IsPOWER9 bool // ISA v3.00 (POWER9)
168 // S390X contains the supported CPU features of the current IBM Z
169 // (s390x) platform. If the current platform is not IBM Z then all
170 // feature flags are false.
172 // S390X is padded to avoid false sharing. Further HasVX is only set
173 // if the OS supports vector registers in addition to the STFLE
174 // feature bit being set.
177 HasZARCH bool // z/Architecture mode is active [mandatory]
178 HasSTFLE bool // store facility list extended
179 HasLDISP bool // long (20-bit) displacements
180 HasEIMM bool // 32-bit immediates
181 HasDFP bool // decimal floating point
182 HasETF3EH bool // ETF-3 enhanced
183 HasMSA bool // message security assist (CPACF)
184 HasAES bool // KM-AES{128,192,256} functions
185 HasAESCBC bool // KMC-AES{128,192,256} functions
186 HasAESCTR bool // KMCTR-AES{128,192,256} functions
187 HasAESGCM bool // KMA-GCM-AES{128,192,256} functions
188 HasGHASH bool // KIMD-GHASH function
189 HasSHA1 bool // K{I,L}MD-SHA-1 functions
190 HasSHA256 bool // K{I,L}MD-SHA-256 functions
191 HasSHA512 bool // K{I,L}MD-SHA-512 functions
192 HasSHA3 bool // K{I,L}MD-SHA3-{224,256,384,512} and K{I,L}MD-SHAKE-{128,256} functions
193 HasVX bool // vector facility
194 HasVXE bool // vector-enhancements facility 1
204 // options contains the cpu debug options that can be used in GODEBUG.
205 // Options are arch dependent and are added by the arch specific initOptions functions.
206 // Features that are mandatory for the specific GOARCH should have the Required field set
207 // (e.g. SSE2 on amd64).
210 // Option names should be lower case. e.g. avx instead of AVX.
214 Specified bool // whether feature value was specified in GODEBUG
215 Enable bool // whether feature should be enabled
216 Required bool // whether feature is mandatory and can not be disabled
219 func processOptions() {
220 env := os.Getenv("GODEBUG")
224 i := strings.IndexByte(env, ',')
228 field, env = env[:i], env[i+1:]
230 if len(field) < 4 || field[:4] != "cpu." {
233 i = strings.IndexByte(field, '=')
235 print("GODEBUG sys/cpu: no value specified for \"", field, "\"\n")
238 key, value := field[4:i], field[i+1:] // e.g. "SSE2", "on"
247 print("GODEBUG sys/cpu: value \"", value, "\" not supported for cpu option \"", key, "\"\n")
252 for i := range options {
253 options[i].Specified = true
254 options[i].Enable = enable || options[i].Required
259 for i := range options {
260 if options[i].Name == key {
261 options[i].Specified = true
262 options[i].Enable = enable
267 print("GODEBUG sys/cpu: unknown cpu feature \"", key, "\"\n")
270 for _, o := range options {
275 if o.Enable && !*o.Feature {
276 print("GODEBUG sys/cpu: can not enable \"", o.Name, "\", missing CPU support\n")
280 if !o.Enable && o.Required {
281 print("GODEBUG sys/cpu: can not disable \"", o.Name, "\", required CPU feature\n")
285 *o.Feature = o.Enable